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3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Arithmetic Logic Unit
4.3.3. Multipy and Divide Units
4.3.4. Floating-Point Unit
4.3.5. Custom Instruction
4.3.6. Instruction Cycles
4.3.7. Reset and Debug Signals
4.3.8. Control and Status Registers
4.3.9. Trap Controller (CLINT)
4.3.10. Memory and I/O Organization
4.3.11. RISC-V based Debug Module
4.3.12. Error Correction Code (ECC)
4.3.13. Branch Prediction
4.3.14. Lockstep Module
4.3.9.1.1. Machine Status Register (mstatus)
4.3.9.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.9.1.3. Machine Interrupt Register (mip and mie)
4.3.9.1.4. Machine Exception Program Counter Register (mepc)
4.3.9.1.5. Machine Cause Register (mcause)
4.3.9.1.6. Machine Trap Value Register (mtval)
4.3.9.1.7. Machine Second Trap Value Register (mtval2)
3.3.8.4.2. Exit Debug Mode
Executing the dret instruction in Debug Mode changes pc to the value stored in dpc. The processor then enters Machine Mode and exits Debug Mode.