Nios® V Processor Reference Manual

ID 683632
Date 1/27/2025
Public

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Document Table of Contents

3.3.8.4.1. Enter Debug Mode

You can enter the Debug Mode, as specified in the RISC-V architecture specification, in the following ways:

  1. Halt from Debug Module
  2. Software breakpoints
  3. Trigger or Hardware breakpoint
Upon entering Debug Mode, Nios® V processor completes the instruction in W-stage. By the order of priority, instruction in M-stage, E-stage, D-stage or F-stage takes the interrupt.
  • When there is a valid instruction, Program Counter writes to the Debug Program Counter, .dpc.

  • If the instruction in M-stage is not valid, then instruction in E-stage takes the interrupt and so on and so forth.

  • If there is no valid instruction in the pipeline, the Program Counter for the next instruction writes to the Debug Program Counter, .dpc.

Note: For branches, the next Program Counter depends on whether a branch was taken or not taken, and whether the branch prediction (if any) was correct.