Visible to Intel only — GUID: ado1734057313941
Ixiasoft
3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Arithmetic Logic Unit
4.3.3. Multipy and Divide Units
4.3.4. Floating-Point Unit
4.3.5. Custom Instruction
4.3.6. Instruction Cycles
4.3.7. Reset and Debug Signals
4.3.8. Control and Status Registers
4.3.9. Trap Controller (CLINT)
4.3.10. Memory and I/O Organization
4.3.11. RISC-V based Debug Module
4.3.12. Error Correction Code (ECC)
4.3.13. Branch Prediction
4.3.14. Lockstep Module
4.3.9.1.1. Machine Status Register (mstatus)
4.3.9.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.9.1.3. Machine Interrupt Register (mip and mie)
4.3.9.1.4. Machine Exception Program Counter Register (mepc)
4.3.9.1.5. Machine Cause Register (mcause)
4.3.9.1.6. Machine Trap Value Register (mtval)
4.3.9.1.7. Machine Second Trap Value Register (mtval2)
Visible to Intel only — GUID: ado1734057313941
Ixiasoft
4.3.11.1.3. Debug Module Register
The Debug Module registers are accessible over the DMI bus only. Each register has a fixed address and developed based on the RISC-V Debug Specification 0.13.2, with JTAG DTM. The Debugger can determine the register implementation status by writing to or reading from the Debug Module registers. Unimplemented registers return 0 when read.
Address | Name | Description |
---|---|---|
0x04 | Abstract Data 0 (data0) | Refer to Abstract Commands. |
0x05 | Abstract Data 1 (data1) | Refer to Abstract Commands. |
0x10 | Debug Module Control (dmcontrol) |
|
0x11 | Debug Module Status (dmstatus) |
|
0x12 | Hart Info (hartinfo) |
|
0x14 | Hart Array Window Select (hawindowsel) | Unimplemented register. Nios® V processor contains a single hart only. |
0x15 | Hart Array Window (hawindow) | Unimplemented register. Nios® V processor contains a single hart only. |
0x16 | Abstract Control and Status (abstractcs) |
Refer to Abstract Commands. |
0x17 | Abstract Command (command) | Refer to Abstract Commands. |
0x18 | Abstract Command Autoexec (abstractauto) | Unimplemented register. |
0x19 ~ 0x1c | Configuration String Pointers (confstrptr) | Unimplemented registers. |
0x1d | Next Debug Module (nextdm) | Unimplemented register. There is only a single DM. |
0x20 ~ 0x27 | Program Buffer 0 to 7 | Refer to Program Buffer. |
0x30 | Authentication Data | 0x0 |
0x37 ~ 0x3f | System Bus Registers | Unimplemented registers. System Bus is not supported. |
0x40 | Halt Summary 0 | LSB reflects halt status of the Nios® V processor. |