Nios® V Processor Reference Manual

ID 683632
Date 1/27/2025
Public
Document Table of Contents

4.3.11.1.3. Debug Module Register

The Debug Module registers are accessible over the DMI bus only. Each register has a fixed address and developed based on the RISC-V Debug Specification 0.13.2, with JTAG DTM. The Debugger can determine the register implementation status by writing to or reading from the Debug Module registers. Unimplemented registers return 0 when read.

Table 117.  Debug Module Register
Address Name Description
0x04 Abstract Data 0 (data0) Refer to Abstract Commands.
0x05 Abstract Data 1 (data1) Refer to Abstract Commands.
0x10 Debug Module Control (dmcontrol)
  • There is a single hart selected.
  • hartsel is 0.
0x11 Debug Module Status (dmstatus)
  • Supports implicit ebreak instruction after Program Buffer execution. Authentication is not implemented. authenticated and authbusy hardwired to 1.
  • confstrptr is not relevant to configuration string.
  • Halt-on-reset functionality is not supported.
  • Version = 3
0x12 Hart Info (hartinfo)
  • No dscratch registers available during Program Buffer execution.
  • data0 holds arg0/return value
  • data1 holds arg1
  • No CSRs dedicated to shadowing the data registers.
0x14 Hart Array Window Select (hawindowsel) Unimplemented register. Nios® V processor contains a single hart only.
0x15 Hart Array Window (hawindow) Unimplemented register. Nios® V processor contains a single hart only.
0x16 Abstract Control and Status (abstractcs)
  • Eight (8) Program Buffer, in 32-bits words.
  • Two (2) data registers

Refer to Abstract Commands.

0x17 Abstract Command (command) Refer to Abstract Commands.
0x18 Abstract Command Autoexec (abstractauto) Unimplemented register.
0x19 ~ 0x1c Configuration String Pointers (confstrptr) Unimplemented registers.
0x1d Next Debug Module (nextdm) Unimplemented register. There is only a single DM.
0x20 ~ 0x27 Program Buffer 0 to 7 Refer to Program Buffer.
0x30 Authentication Data 0x0
0x37 ~ 0x3f System Bus Registers Unimplemented registers. System Bus is not supported.
0x40 Halt Summary 0 LSB reflects halt status of the Nios® V processor.