Nios® V Processor Reference Manual

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ID 683632
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Instruction Cycles 2.3.5. Memory and I/O Organization 2.3.6. Error Correction Code (ECC)
2.3.5. Memory and I/O Organization x
2.3.5.1. Instruction and Data Buses 2.3.5.2. Address Map
2.3.5.1. Instruction and Data Buses x
2.3.5.1.1. Instruction Manager Port 2.3.5.1.2. Data Manager Port 2.3.5.1.3. Choosing a Suitable Interface
2.4. Programming Model x
2.4.1. Privilege Levels
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Instruction Cycles 3.3.6. Trap Controller (CLINT) 3.3.7. Memory and I/O Organization 3.3.8. RISC-V based Debug Module 3.3.9. Error Correction Code (ECC)
3.3.6. Trap Controller (CLINT) x
3.3.6.1. Related Control and Status Register 3.3.6.2. Direct Mode 3.3.6.3. Vectored Mode
3.3.6.1. Related Control and Status Register x
3.3.6.1.1. Machine Status Register (mstatus) 3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec) 3.3.6.1.3. Machine Interrupt Register (mip and mie) 3.3.6.1.4. Machine Exception Program Counter Register (mepc) 3.3.6.1.5. Machine Cause Register (mcause) 3.3.6.1.6. Machine Trap Value Register (mtval)
3.3.6.2. Direct Mode x
3.3.6.2.1. Hardware Implementation 3.3.6.2.2. Software Implementation
3.3.6.3. Vectored Mode x
3.3.6.3.1. Hardware Implementation 3.3.6.3.2. Software Implementation
3.3.7. Memory and I/O Organization x
3.3.7.1. Instruction and Data Buses 3.3.7.2. Address Map
3.3.7.1. Instruction and Data Buses x
3.3.7.1.1. Instruction Manager Port 3.3.7.1.2. Data Manager Port 3.3.7.1.3. Choosing a Suitable Interface
3.3.8. RISC-V based Debug Module x
3.3.8.1. Debug Module 3.3.8.2. Abstract Commands 3.3.8.3. Program Buffer 3.3.8.4. Debug Mode 3.3.8.5. Hardware Trigger Module 3.3.8.6. JTAG Debug Transport Module 3.3.8.7. Nios® V Processor Implementation
3.3.8.1. Debug Module x
3.3.8.1.1. Reset/Halt/Run Control 3.3.8.1.2. Hart States 3.3.8.1.3. Debug Module Register
3.3.8.2. Abstract Commands x
3.3.8.2.1. Access Register Command 3.3.8.2.2. Using Access Register Command
3.3.8.3. Program Buffer x
3.3.8.3.1. Using Program Buffer
3.3.8.4. Debug Mode x
3.3.8.4.1. Enter Debug Mode 3.3.8.4.2. Exit Debug Mode 3.3.8.4.3. Core Debug Registers
3.3.8.5. Hardware Trigger Module x
3.3.8.5.1. Trigger Registers 3.3.8.5.2. Type of Address/Data Match Triggers 3.3.8.5.3. Using Triggers
3.3.8.6. JTAG Debug Transport Module x
3.3.8.6.1. JTAG DTM Registers 3.3.8.6.2. Accessing Debug Module Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field 3.4.2.2. Memory Mapped Registers Fields
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Instruction Cycles 4.3.7. Reset and Debug Signals 4.3.8. Control and Status Registers 4.3.9. Trap Controller (CLINT) 4.3.10. Memory and I/O Organization 4.3.11. RISC-V based Debug Module 4.3.12. Error Correction Code (ECC) 4.3.13. Branch Prediction 4.3.14. Lockstep Module
4.3.4. Floating-Point Unit x
4.3.4.1. IEEE 754 Exception Conditions 4.3.4.2. Floating Point Operations
4.3.4.2. Floating Point Operations x
4.3.4.2.1. Floating Point Classification
4.3.9. Trap Controller (CLINT) x
4.3.9.1. Related Control and Status Register 4.3.9.2. Direct Mode 4.3.9.3. Vectored Mode
4.3.9.1. Related Control and Status Register x
4.3.9.1.1. Machine Status Register (mstatus) 4.3.9.1.2. Machine Trap-Vector Base-Address Register (mtvec) 4.3.9.1.3. Machine Interrupt Register (mip and mie) 4.3.9.1.4. Machine Exception Program Counter Register (mepc) 4.3.9.1.5. Machine Cause Register (mcause) 4.3.9.1.6. Machine Trap Value Register (mtval) 4.3.9.1.7. Machine Second Trap Value Register (mtval2)
4.3.9.2. Direct Mode x
4.3.9.2.1. Hardware Implementation 4.3.9.2.2. Software Implementation
4.3.9.3. Vectored Mode x
4.3.9.3.1. Hardware Implementation 4.3.9.3.2. Software Implementation
4.3.10. Memory and I/O Organization x
4.3.10.1. Instruction and Data Buses 4.3.10.2. Address Map 4.3.10.3. Cache Memory 4.3.10.4. Tightly Coupled Memory
4.3.10.1. Instruction and Data Buses x
4.3.10.1.1. Instruction Manager Port 4.3.10.1.2. Data Manager Port
4.3.10.3. Cache Memory x
4.3.10.3.1. Instruction Cache 4.3.10.3.2. Data Cache 4.3.10.3.3. Configurable Cache Memory 4.3.10.3.4. Bypassing Cache (Peripheral Region) 4.3.10.3.5. Using Cache Memory Effectively
4.3.10.4. Tightly Coupled Memory x
4.3.10.4.1. Instruction and Data Tightly Coupled Memory 4.3.10.4.2. Accessing Tightly Coupled Memory 4.3.10.4.3. Using Tightly Coupled Memory Effectively
4.3.11. RISC-V based Debug Module x
4.3.11.1. Debug Module 4.3.11.2. Abstract Commands 4.3.11.3. Program Buffer 4.3.11.4. Debug Mode 4.3.11.5. Hardware Trigger Module 4.3.11.6. JTAG Debug Transport Module 4.3.11.7. Nios® V Processor Implementation
4.3.11.1. Debug Module x
4.3.11.1.1. Reset/Halt/Run Control 4.3.11.1.2. Hart States 4.3.11.1.3. Debug Module Register
4.3.11.2. Abstract Commands x
4.3.11.2.1. Access Register Command 4.3.11.2.2. Using Access Register Command
4.3.11.3. Program Buffer x
4.3.11.3.1. Using Program Buffer
4.3.11.4. Debug Mode x
4.3.11.4.1. Enter Debug Mode 4.3.11.4.2. Exit Debug Mode 4.3.11.4.3. Core Debug Registers
4.3.11.5. Hardware Trigger Module x
4.3.11.5.1. Trigger Registers 4.3.11.5.2. Type of Address/Data Match Triggers 4.3.11.5.3. Using Triggers
4.3.11.6. JTAG Debug Transport Module x
4.3.11.6.1. JTAG DTM Registers 4.3.11.6.2. Accessing Debug Module Interface
4.3.12. Error Correction Code (ECC) x
4.3.12.1. ECC Interface 4.3.12.2. ECC Error Injection 4.3.12.3. Affected CSR during ECC Event
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping (CLINT)
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping (CLINT) x
4.4.2.1. Control and Status Register Field (CLINT) 4.4.2.2. Memory Mapped Registers Fields
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

4.3.10.3.4. Bypassing Cache (Peripheral Region)

The Nios® V/g architecture has two peripheral regions for bypassing the caches. Nios® V/g cores optionally support the peripheral region mechanism to indicate cacheability. In the Platform Designer, the peripheral region cache-ability mechanism allows you to specify a region of address space that is non-cacheable. The peripheral region is any integer power of 2 bytes, from a minimum of 64 kilobytes up to a maximum of 2 gigabytes, and must be located at a base address aligned to the size of the peripheral region. The peripheral region is available provided that an MMU is not present. The peripheral regions are non-bursting.
Note: Any accesses to the Nios® V processor's debug module or timer module are non-cacheable.
Note: You must place the peripherals driven by the Nios® V/g processor within a defined peripheral region to achieve cache bypass, which is required by a standard design implementation.
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