F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 9/26/2022

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2.5. Simulating the IP Core

You can simulate your Interlaken IP variation using any of the vendor-specific IEEE encrypted functional simulation models which are available in the new <instance name>/sim/<simulator> subdirectory of your project directory.

The F-Tile Interlaken Intel® FPGA IP core supports the following simulators:
  • Synopsys* VCS* and VCS* MX
  • Siemens* EDA QuestaSim*
  • Cadence* Xcelium*

The F-Tile Interlaken Intel® FPGA IP core generates a Verilog HDL and VHDL simulation model and testbench. The IP core parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP core, but the IP core design example does not support a VHDL simulation model or testbench.

For more information about functional simulation models for Intel FPGA IP cores, refer to the Simulating Intel FPGA Designs chapter in Intel Quartus Prime Pro Edition User Guide: Third-party Simulation.