F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

3. Parameter Settings

You customize the F-Tile Interlaken Intel® FPGA IP core using the IP parameter editor.
Table 12.  Main: General
Parameter Supported Values Default Setting Description
PMA Type FGT

FHT

 FHT
Specifies the type of transceiver for your design.
  • FGT is a 53.125G transceiver
  • FHT is a 106.25G transceiver
Note: This parameter is only available when the Transceiver mode is PAM4.
Meta fame length 128-8192 2048

Specifies the meta frame length in 64-bit (8-byte) words. Must be a power of two.

Smaller values shorten the time to achieve lock. Larger values reduce the overhead while transferring data, after the clock data recover (CDR) circuit achieves lock.

Number of lanes 4

6

8

10

12

 8 This parameter specifies the number of lanes available for Interlaken communication.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to Table: IP Supported Combinations of Number of Lanes and Data Rate in this document.

Data rate (Gbps) 6.25

10.3125

12.5

25.78125

26.5625

 12.5 Gbps This parameter specifies the data rate on each lane.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to Table: IP Supported Combinations of Number of Lanes and Data Rate in this document.

Transceiver reference clock frequency Multiple 156.25 MHz This parameter specifies the expected frequency of the pll_ref_clk input clock.

If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.

Enable Interlaken Look-aside mode On

Off

 Off Enable this option to configure the IP core in Interlaken Look-aside mode.
Enable M20K ECC support On

Off

 Off This parameter specifies whether your Interlaken IP variation supports the ECC feature in the M20K memory blocks that are configured as part of the IP.

You can turn this parameter on to enable single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP. This feature enhances data reliability but increases latency and resource utilization.

Enable EFIFO support On

Off

 Off Enable this parameter when the SystemPLL clock frequency is not same as the PMA clock frequency.
Note: You must enable EFIFO for FHT PMAs due to existence of PPM between FHT and F-tile SystemPLL when the refclk source is not shared.
System PLL clock frequency User defined 830.078125 MHz Set the desired SystemPLL clock frequency when the SystemPLL clock frequency is not same as the PMA clock frequency. The SystemPLL clock frequency must be higher than transceiver clock frequency.
Note: This parameter is only available when the Enable EFIFO support is turned on. This feature is only supported for PAM4 mode.
This value must match the SystemPLL clock which is connected to the IP core.
System PLL reference clock frequency Multiple 156.25 MHz Set the desired SystemPLL reference clock frequency when the SystemPLL clock frequency is not same as the PMA clock frequency.
Note: This parameter is only available for design example generation when the Enable EFIFO support is turned on.
Enable debug endpoint for Datapath and PMA Avalon® memory-mapped interface On

Off

 Off When turned On, the F-Tile Interlaken Intel® FPGA IP core includes an embedded Debug Endpoint that internally connects the Avalon memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the PMA interface block. it can perform certain tests and debug functions through JTAG using the System Console. This option may require that you include a jtag_debug link in the system.
Table 13.  In-Band Flow Control
Parameter Supported Values Default Setting Description
Include in-band flow control functionality On

Off

 Off This parameter specifies whether your Interlaken IP includes an in-band flow control block.
Number of calendar pages 1

2

4

8

16

 1 This parameter specifies the number of 16-bit pages of in-band flow control data that your Interlaken IP supports. This parameter is available if you turn on Include in-band flow control functionality.

Each 16-bit calendar page includes 16 in-band flow control bits. The application determines the interpretation of the in-band flow control bits. The IP supports a maximum of 256 channels with in-band flow control.

If your design requires a different number of pages, select the lowest supported number of pages which is larger than the number required, and ignore any unused pages. For example, if your configuration requires three in-band flow control calendar pages, you can set this parameter to 4 and use pages 3, 2, and 1 while ignoring page 0.
Table 14.  Transceiver Settings
Transceiver Settings Parameter Supported Values Default Setting Description
TX scrambler seed — 0x3ab1278890105cd

This parameter specifies the initial scrambler state. If you configure a single Interlaken IP on your device, you can use the default value of this parameter.

If you configure multiple Interlaken IPs, you must use a different initial scrambler state for each IP. Select random values for each Interlaken IP. Each scrambler seed should have an approximately even mix of ones and zeros. The scrambler seeds should differ from the other scramblers in multiple spread out bit positions.

Transceiver mode NRZ

PAM4

 NRZ Specifies the transceiver modulation mode.
Table 15.  User Data Transfer Interface
Parameter Supported Values Default Setting Description
Transfer mode selection Packet

Interleaved

 Packet Supports two modes for packet transfer flexibility and ASIC/ASSP/FPGA/SoC interoperability.
Number of Segments 1

2

4

 1 This parameter enables 1, 2, or 4 segments depending on the total number of words.
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