F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 9/26/2022

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Document Table of Contents Transmit Path Blocks

The Interlaken IP core transmit data path has the following four main functional blocks:
  • TX Transmit Buffer
  • TX MAC
  • TX PCS
  • TX PMA

TX Transmit Buffer

The Interlaken IP core TX transmit buffer aligns the incoming user application data, itx_din_words in the IP core internal format.


The Interlaken IP core TX MAC performs the following functions:
  • Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet interleaving in the Interlaken protocol.
  • Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
  • Calculates and inserts CRC24 bits in all burst and idle words.
  • Inserts calendar data in all burst and idle words, if you configure in-band flow control.
  • Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0.
  • Stripes and de-stripes between the user data (data width) and the number of lanes. Refer to Table 2: IP Core Theoretical Raw Aggregate Bandwidth in this document for more information on supported combinations.
  • Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width.


The FPGA soft logic implements TX PCS. In PAM4 mode, the IP core contain a soft logic transcoder block to work with RS FEC (544, 514) of the TX PMA. The Interlaken IP core TX PCS block performs the following functions for each lane:
  • Inserts the meta frame words in the incoming data stream.
  • Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
  • Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
  • Performs 64B/67B encoding.
  • Performs asynchronous operations and transmission lane alignment using TX Align FIFO.
  • Performs the Interlaken transcoding function to support the RS FEC (544, 514) of the TX PMA in PAM4 mode applications.


The Interlaken IP core TX PMA serializes the data and sends it out on the Interlaken link. TX PMA contains RS FEC block in PAM4 mode and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each FEC core block serves four streams, using the same system clock and resets. For further details on F-tile FEC Core, refer to F-tile Architecture and PMA/FEC Direct PHY IP User Guide.
Note: For a 10-lane configuration design, the F-tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew. Therefore, resources of 12-lane configuration are consumed in a 10-lane configuration.