F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 9/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1. About the F-Tile Interlaken Intel® FPGA IP Core

Updated for:
Intel® Quartus® Prime Design Suite 22.3
IP Version 5.0.0

Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The F-Tile Interlaken Intel® FPGA IP core implements the Interlaken Protocol Specification, v1.2. The F-Tile Interlaken Intel® FPGA IP core supports multiple combinations of number of lanes (2 to 12) and lane rates from 6.25 gigabits per second (Gbps) to 53.125 Gbps providing raw bandwidth up to 300 Gbps.

Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken IP incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.

Figure 1. Typical Interlaken Application

Interlaken Look-aside is a scalable protocol that allows interoperability between a datapath device and a Look-aside co-processor with packet transfer rates up to 300 Gbps. Interlaken Look-aside mode is supported starting version 21.4 of the Intel® Quartus® Prime Pro Edition software.