126.96.36.199. Transmit User Data Interface Example
Packet Mode Transfer ExampleThis example illustrates the expected behavior of the Interlaken Look-aside application interface transmit signals during a packet transfer in packet mode.
In cycle 5, the IP core detects assertion of itx_idle and all of itx_idle bits are asserted indicating that eight idle control words can be inserted in this slot.
In cycle 6, itx_valid signal is deasserted indicating that all of other signals are not valid. itx_valid signal is deasserted because TX_CREDIT_LATENCY cycles before, itx_credit was deasserted.
In cycle 7, itx_valid is asserted and itx_idle is 0x0, which indicates itx_sop, itx_eopbits, and itx_din_words signals. Assert the itx_sop to indicate the start of packet. Burst control word can be inserted at this location and seven data words in itx_din_words[447:0] should follow it. Corresponding itx_chan indicates the channel associated with this data packet following the control word. The IP ignores the rest of itx_chan [6:0] bits.
In cycle 8, the transfer of data packet should be terminated since itx_eopbits[3:0] is not zero. The seven data words in itx_data[511:0] should be transferred as a part of data packet. itx_chan is invalid in this cycle because itx_sop bits are not set. itx_eopbits[3:0] can be set to 4'b1000 to indicate the end of packet and last word contains 8 bytes. This eopbits field can be set to EOP_Format field of following burst control words.
In cycle 9, the itx_valid should be de-asserted because before the TX_CREDIT_LATECNY cycles, itx_credit was deasserted.
In cycle 10, the transfer of new data packet starts and this can be terminated since itx_eopbits[3:0] is not zero. In this cycle, user sends 49 bytes to the IP core. The itx_eopbits[3:0]= 4'b0001 indicates that the last word (tx_data[63:0]) only contains one byte. This itx_eopbits[3:0] value can be set to EOP_Format field of following IDLE control word.
In cycle 11, itx_valid should be asserted because before TX_CREDIT_LATENCY cycles, itx_credit was deasserted.
In cycle 12, user logic asserts itx_idle[7:0] indicating that it wants to terminate the data burst and send eight idle control words.
- In cycle 7, the IP core receives burst control word and 56 bytes of valid data (data 1)
- In cycle 8, the IP core receives 64 bytes of valid data (data 2)
The total packet length for the first packet is 56 + 64 = 120 bytes.
- In cycle 10, the IP core receives another burst control word and 49 bytes of valid data (data 3)
The total packet length for the second packet is 49 bytes.