1.5. Simulating the Design Example
Figure 6. Procedure
- Change to the testbench simulation directory, pcie_example_design_tb.
- Run the simulation script for the simulator of your choice. Refer to the table below.
- Analyze the results.
Simulator | Working Directory | Instructions |
---|---|---|
ModelSim* | <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/ |
|
VCS* | <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs |
|
NCSim* | <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/cadence |
|
Xcelium* Parallel Simulator | <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/xcelium |
|
The DMA testbench completes the following tasks:
- Writes to the Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
- Reads from Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
- Verifies the data using the shmem_chk_ok task.
- Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MRd request to the PCIe* address space in host memory.
- Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MWr request to PCIe* address space in host memory. This MWr uses the data from the previous MRd.
- Verifies the data using the shmem_chk_ok task.
The simulation reports, "Simulation stopped due to successful completion" if no errors occur.
Figure 7. Partial Transcript from Successful Simulation Testbench