Intel® Stratix® 10 H-tile and L-tile Avalon® Memory-mapped Hard IP for PCI Express* Design Example User Guide
A.1. Intel® Stratix® 10 H-tile and L-tile Avalon® memory mapped Hard IP for PCI Express* Design Example User Guide Revision History
| Date | Software Version | Changes |
|---|---|---|
| 2022.03.07 | 20.3 | Added the section Hardware and Software Requirements. |
| 2020.10.12 | 20.3 | Removed references to the Simple DMA design example as that design example is no longer available. |
| November 2017 | 17.1 | Made the following changes:
|
| May 2017 | Quartus®Prime Pro v17.1 Stratix 10 ES Editions | Initial release. |