DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameter 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. DisplayPort Transceiver Reconfiguration Flow 2.10. Transceiver Lane Configurations
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.7. Hardware Setup

The DisplayPort Intel® FPGA IP design example is 4Kp60 capable and performs a loop-through for a standard DisplayPort video stream.
  1. To run the hardware test, connect a DisplayPort-enabled source device to the DisplayPort FMC daughter card sink input.
  2. The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core.
  3. The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data.
    Note: You require the clock recovery feature to produce video without using a frame buffer.
  4. The clock recovery core then sends the video data to the DisplayPort source and the Transceiver Native PHY TX block.
  5. Connect the DisplayPort FMC daughter card source port to a monitor to display the image.
Table 21.  On-board User LED Functions
LEDs Function
USER_LED[0]

This LED indicates that the source is successfully lane-trained.

At this point, the IP core asserts rx0_vid_locked.

USER_LED[1]

This LED indicates that the source Transceiver PLL is locked at the link training data rate.

USER_LED[3:2] These LEDs indicate the RX link rate.
  • 2'b00 = RBR
  • 2'b01 = HBR
  • 2'b10 = HBR2
  • 2'b11 = HBR3
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