2. Parallel Loopback Design Examples
The DisplayPort Intel® FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Design Example | Designation | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|---|
DisplayPort SST parallel loopback with PCR | DisplayPort SST | HBR3, HBR2, HBR, and RBR | Simplex | Parallel with PCR |
DisplayPort SST parallel loopback without PCR | DisplayPort SST | HBR3, HBR2, HBR, and RBR | Simplex | Parallel without PCR |
DisplayPort MST parallel loopback with PCR | DisplayPort MST | HBR3, HBR2, HBR, and RBR | Simplex | Parallel with PCR |
DisplayPort MST parallel loopback without PCR | DisplayPort MST | HBR3, HBR2, HBR, and RBR | Simplex | Parallel without PCR |
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