DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameter 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. DisplayPort Transceiver Reconfiguration Flow 2.10. Transceiver Lane Configurations
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features

The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source with or without Pixel Clock Recovery (PCR).
Figure 6.  Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback with PCR
  • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned off and the standard VSYNC/HSYNC/DE video interface is used.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The IOPLL drives the video clock at a fixed frequency (in this case, 160 MHz).
  • If DisplayPort sink’s MAX_LINK_RATE is configured to HBR2 and PIXELS_PER_CLOCK is configured to Dual, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
  • The design uses the pixel recovery clock (PCR) to recover the pixel clock according to the received MSA information from the sink and converts the RX parallel video interface to the standard VSYNC/HSYNC/DE interface.
  • The PCR output drives the source video interface and encodes to the DisplayPort main link before transmitting to the monitor.
  • The recovered clock drives the TX video clock.
Figure 7.  Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback without PCR
  • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned on (“1”) and the video image interface is used.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor.
  • The IOPLL drives both the DisplayPort sink and source video clocks at a fixed frequency.
  • If DisplayPort sink and source's MAX_LINK_RATE parameter is configured to HBR2 and PIXELS_PER_CLOCK is configured to Dual, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
Table 8.  Design Example Variant Comparison
Design Example PCR Module Enable Video Image Interface Adaptive Sync Video Interface
DisplayPort SST parallel loopback with PCR Required No Not supported Standard VSYNC/HSYNC/DE interface (txN_video_in)
DisplayPort SST parallel loopback without PCR Not required Yes Supported Video Image Interface (txN_video_in_im)
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