DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683603
Date 9/28/2020
Public

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4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Date Intel® Quartus® Prime Version Intel® FPGA IP Version Changes
2020.09.28 20.3 19.4.0
  • Updated and renamed the Configuring Single or Dual Lanes section to Transceiver Lane Configurations.
  • Added pin assignments for Bitec FMC revision 10 in the Transceiver Lane Configurations section.
  • Updated the pin assignments for Bitec FMC revision 8 or earlier, and revision 11 with transceiver Avalon® memory-mapped interface group information in the Transceiver Lane Configurations section.
2020.04.13 20.1 19.3.0
  • Updated the Bitec DisplayPort card revision and the IP version in the local parameter in the RTL file at <project directory>/rtl/c10_dp_demo.v and the software config.h file in the Compiling and Testing the Design section.
  • Updated the description for the fmca_la_tx_n_12 signal and added a new signal, fmca_la_tx_p_14 for DisplayPort FMC daughter card pins in the Interface Signals and Parameters section.
  • Replaced the description about the Parade Tech PS8460 Retimer signals with the FMC On-board Retimer Reconfiguration Interface signals in the Interface Signals and Parameters section.
2019.07.30 19.2 19.1.0
  • Added information about the DisplayPort MST parallel loopback with and without a PCR module design examples in the DisplayPort Intel® FPGA IP Design Example Quick Start Guide section.
  • Updated the files and folders in the Directory Structure section.
  • Added support for the Bitec DisplayPort FMC daughter card revision 11 in the Hardware and Software Requirements section.
  • Added information about the DisplayPort MST parallel loopback with and without a PCR module design examples in the Generating the Design, DisplayPort Intel® FPGA IP Design Example Parameters, and DisplayPort Intel® FPGA IP Design Example Detailed Description sections.
  • Updated the Regenerating ELF File section to include information about WSL and provided a link to the Nios II Software Developer Handbook.
  • Updated the Compiling and Testing the Design section to include information about the Bitec DisplayPort FMC daughter card revision 11, channel mapping, and clock controller setting.
  • Updated the Configuring Single or Dual Lanes section with information about the Bitec DisplayPort FMC daughter card revision 11.
2019.04.05 19.1 19.1
  • Removed the /altera_avalon_i2c file from the Directory Structure section. It is not added in the core folder.
  • Updated the Directory Structure section to add the Xcelium Parallel simulator files.
  • Added instructions to run simulation using the Xcelium Parallel simulator in the Simulating the Design section.
  • Edited the DisplayPort Design Example Supported EDA Simulators table in the Simulation Testbench section to include Xcelium Parallel simulator and the supported platforms.
  • Moved the .c and .h software files to a new folder in the Directory Structure section. These files are now in the dp_demo subfolder in version 19.1 of the DisplayPort Intel® FPGA IP.
  • Updated the Bitec DisplayPort FMC daughter card local parameter in the Compiling and Testing the Design section.
  • Edited the note about CRC calculation in the Simulation Testbench section. To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
  • Updated the frequency rate for HBR quad symbols per clock to 67.5 for the RX and TX Transceiver Clockout descriptions in the Clocking Scheme section.
  • Added the Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback with Adaptive Sync Support section to provide guidelines to add the Adaptive Sync feature,
  • Added the Configuring Single or Dual Lanes section to provide guidelines to make the correct pin assignments for single and dual lanes.
2017.12.25 17.1.1 17.1.1 Initial release.