DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683603
Date 9/28/2020
Public

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1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Intel® Quartus® Prime Pro Edition software and open <project directory>/quartus/c10_dp_demo.qpf.
    Note:

    The latest Bitec DisplayPort FMC daughter card has different schematics compared to the earlier revisions.

    Table 4.  RX Transceiver Channel Mapping
    Parameter Revisions 8 and Earlier Revision 10 Revision 11 Description
    Polarity Not inverted Inverted Inverted
    • When RX polarity is inverted, each lane at the rx_polinv port of the Native PHY is driven to 1 in the rx_phy_top.v file.
    • When RX polarity is not inverted, each lane at the rx_polinv port of the Native PHY is driven to 0 in the rx_phy_top.v file.
    Order Not reversed Not reversed Reversed The rx_parallel_data port of the Native PHY is directly mapped to the rx_parallel_data port of the DisplayPort IP.
    Table 5.  TX Transceiver Channel Mapping
    Parameter Revisions 8 and Earlier Revision 10 Revision 11 Description
    Polarity Inverted Not inverted Not inverted
    • When TX polarity is inverted, each lane at the tx_polinv port of the Native PHY is driven to 1 in the tx_phy_top.v file.
    • When TX polarity is not inverted, each lane at the tx_polinv port of the Native PHY is driven to 0 in the tx_phy_top.v file.
    Order Reversed Not reversed Not reversed
    • When the lane order is reversed, the data input at the tx_parallel_data port of the Native PHY is swapped in the tx_phy_top.v file based on the lane count configuration.
    • When the lane order is not reversed, tx_parallel_data port of the Native PHY is directly mapped to the tx_parallel_data port of the DisplayPort IP.
    To support all revisions, the design example top level RTL file at <project directory>/rtl/c10_dp_demo.v and the software config.h file include a local parameter for you to select the FMC revision.

    DisplayPort Intel® FPGA IP version 19.3.0:

    localparam BITEC_DP_CARD_REV = 2;
    // 0 = Bitec FMC DP card rev.4 - 8,
    // 1 = rev.10
    // 2 = rev.11
    in <project>/software/dp_demo/config.h:
    #define BITEC_DP_CARD_REV 2
    // set to 0 = Bitec FMC DP card rev.4 - 8 
    // set to 1 = Bitec FMC DP card rev.10
    // set to 2 = Bitec FMC DP card rev.11
    The default value is 2. If the config.h file is updated, you must run build_sw.sh in the script folder before compiling the Intel® Quartus® Prime Pro Edition project to ensure the software is effective.
  3. Click Processing > Start Compilation.
  4. Open the Clock Controller parameter editor, and set the clock frequency in the Si5332(U64) tab.
    Figure 5. Clock Controller Parameter Editor
  5. After successful compilation, the Intel® Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
  6. Connect the DisplayPort RX connector on the Bitec daughter card to an external video source, such as the graphics card on a PC.
  7. Connect the DisplayPort TX connector on the Bitec daughter card to a video analyzer or a DisplayPort sink device, such as a PC monitor.
  8. Ensure all switches on the development board are in default position.
  9. Configure the selected Intel® Cyclone® 10 GX device on the development board using the generated .sof file (Tools > Programmer ).
  10. The DisplayPort sink device displays the video generated from the video source.

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