Intel Agilex® 7 Hard Processor System Component Reference Manual

ID 683581
Date 4/10/2023
Document Table of Contents

3.5. Lightweight HPS-to-FPGA AXI* Master Interface

The lightweight HPS‑to‑FPGA AXI* master interface, h2f_lw_axi_master, is connected to a Mentor Graphics AXI* master BFM for simulation with an instance name of h2f_lw_axi_master_inst. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to h2f_lw_axi_clock clock.

Table 24.  Configuration of Lightweight HPS-to-FPGA AXI* Master BFM



AXI* Address Width

20 - 21

AXI* Read and Write Data Width


AXI* ID Width


You control and monitor the AXI* master BFM by using the BFM API.