Intel Agilex® 7 Hard Processor System Component Reference Manual

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ID 683581
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel Agilex® 7 Hard Processor System Component 2. Configuring the Intel Agilex® 7 Hard Processor System Component 3. Simulating the Intel Agilex® 7 HPS Component
1. Introduction to the Intel Agilex® 7 Hard Processor System Component x
1.1. Cortex*-A53 MPCore* Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Intel Agilex® 7 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. HPS EMIF 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR Arm* Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.6. Pin MUX and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. Pin Mux Report 2.6.3. EMAC ptp Interface
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
3. Simulating the Intel Agilex® 7 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the Intel Agilex® 7 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. Running the Simulations
3.1.1. Setting Up the HPS Component for Simulation x
3.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
3.1.3. Running the Simulations x
3.1.3.1. Running HPS RTL Simulation 3.1.3.2. Running HPS Post-Fit Simulation
3.1.3.2. Running HPS Post-Fit Simulation x
3.1.3.2.1. Post-Fit Simulation Files 3.1.3.2.2. BFM API Hierarchy Format
3.2. Clock and Reset Interfaces x
3.2.1. Clock Interface 3.2.2. Reset Interface
1. Introduction to the Intel Agilex® 7 Hard Processor System Component
2. Configuring the Intel Agilex® 7 Hard Processor System Component
3. Simulating the Intel Agilex® 7 HPS Component

2.2.2.1. FPGA-to-HPS Slave Interface

The FPGA-to-HPS slave interface allows FPGA masters to issue transactions to the HPS. You can use the:
  • Interface specification drop-down to configure this master interface to AXI-4 or ACE-lite.
  • Enable/Data Width drop-down to configure this master interface's data widths to 128-, 256-, or 512-bit.
  • Interface address width is configurable from 40 bits down to 20 bits, which allows the FPGA fabric to access the majority of the HPS address space. To facilitate masters in the FPGA logic with a smaller address width than the bridge in accessing the HPS address space, you can use the Intel Address Span Extender component.
  • Interface destination configures routing for transactions. This interface supports routing to the Cache Coherency Unit (CCU) directly, SDRAM directly (bypasses the CCU), or a Custom configuration controlled by the FPGA AXI-master.
    Table 3.  Interface Destination Selection
    Selection Description
    CCU
    • Fixed the AxUSER[7:0] to 0x04, the transaction is routed to CCU directly.
    • Supports the coherent and non-coherent accesses from FPGA to SDRAM.
    • All accesses to HPS IO space must use this mode for FPGA visibility.
    SDRAM Direct
    • Fixed the AxUSER[7:0] to 0xE0, the transaction is routed to SDRAM directly.
    • Supports the non-coherent accesses from FPGA to SDRAM.
    • HPS IO space is not visible to FPGA.
    Inband Exposed the AxUSER in the AXI or ACE-Lite interface. You can control through its AXI Master.

For more information, refer to the "Using the Address Span Component Extender" chapter.

When this bridge is enabled, the interfaces f2h_axi_slave, f2h_axi_clock,and f2h_axi_reset are made available.

This interface allows the FPGA to access the majority of the HPS slaves. When configured as an ACE-lite slave, this interface provides a coherent memory interface. Other interface standards in the FPGA fabric, such as connecting to Avalon® Memory Mapped ( Avalon® -MM) interfaces, can be supported through the use of soft logic adapters. The Platform Designer system integration tool automatically generates adapter logic to connect AXI* to Avalon® -MM interfaces.

Note: The hps_emif conduit is enabled when either the AXI or ACE-Lite bridge is selected.

For more information, refer to HPS Bridges section in the Intel Agilex® 7 Hard Processor System Technical Reference Manual.

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