Intel Agilex® 7 Hard Processor System Component Reference Manual

ID 683581
Date 4/10/2023
Document Table of Contents HPS to FPGA User Clocks

Turning on the Enable HPS-to-FPGA User0 clock or Enable HPS-to-FPGA User1 clock option enables one of two available HPS PLL outputs into the FPGA. You can connect a user clock to logic that you instantiate in the FPGA. When you enable a HPS-to-FPGA user clock, the clock frequency field displays the default maximum frequency for the user clock based on the device speed grade selected. User clocks can be manually overridden and driven from peripheral PLL or Main PLL.