Intel® Agilex™ Hard Processor System Component Reference Manual

ID 683581
Date 12/14/2022

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The HPS supports one DDR4 interface.
  • In Intel® Quartus® Prime Pro Edition version 19.2, the HPS EMIF conduit can only be disabled if both the FPGA-to-HPS interface is unused, and the SDRAM tab enable box is unchecked.
  • In Intel® Quartus® Prime Pro Edition version 19.3, the SDRAM tab will be removed, and the HPS EMIF conduit will be enabled or disabled through the FPGA-to-HPS interface used or unused.
Figure 18.  Platform Designer Displaying the hps_emif Conduit for FPGA Interfaces Tab
Figure 19.  Platform Designer Displaying hps_emif in System View
Figure 20.  Platform Designer Displaying hps_emif Conduit for SDRAM Tab
In the following figure, the MPFE path is selected by checking the EMIF_CONDUIT_Enable button so that the HPS can access the DDR4 SDRAM.
Figure 21. Enabling the MPFE path to be connected to the HPS

In the following figure, you can select the MPFE BYPASS mode by setting the FPGA-to-HPS interface to "Unused", and unchecking the EMIF_CONDUIT_Enable button. In this case, the HPS cannot access the DDR4 SDRAM, which allows for the FPGA fabric to directly control the DDR4 SDRAM.

Figure 22. Selecting MPFE BYPASS mode