Intel® Agilex™ Hard Processor System Component Reference Manual

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ID 683581
Date 12/14/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Agilex™ Hard Processor System Component 2. Configuring the Intel® Agilex™ Hard Processor System Component
1. Introduction to the Intel® Agilex™ Hard Processor System Component x
1.1. Cortex*-A53 MPCore* Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Intel® Agilex™ Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. HPS EMIF 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR Arm* Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.6. Pin MUX and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. Pin Mux Report 2.6.3. EMAC ptp Interface
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
1. Introduction to the Intel® Agilex™ Hard Processor System Component
2. Configuring the Intel® Agilex™ Hard Processor System Component

2.7. Generating and Compiling the HPS Component

The process of generating and compiling an HPS design is very similar to the process for any other Platform Designer project. Perform the following steps:

  1. Generate the design with Platform Designer. The generated files include an .sdc file containing clock timing constraints. If simulation is enabled, simulation files are also generated.
    Additionally, while using the FPGA to HPS slave interface in AXI* -4 mode, selecting Load IP-XACT Register Details includes relevant CSR offsets information with an "isPresent" tag in the generated .ip file.
    Figure 29.  Platform Designer Displaying Load IP-XACT Register Details in AXI* -4 Mode
  2. Add <qsys_system_name>.qip to the Intel® Quartus® Prime project. <qsys_system_name>.qip is the Intel® Quartus® Prime IP File for the HPS component, generated by Platform Designer.
    Note: Platform Designer generates pin assignments in the .qip file.
    Figure 30.  Platform Designer Displaying the Pin Assignments
  3. Perform analysis and synthesis with the Intel® Quartus® Prime software.
  4. Compile the design with the Intel® Quartus® Prime software.
  5. Optionally back-annotate the SDRAM pin assignments, to eliminate pin assignment warnings the next time you compile the design.
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