LVDS SERDES FPGA IP Release Notes

Download PDF
ID 683575
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
LVDS SERDES FPGA IP Release Notes
LVDS SERDES FPGA IP Release Notes x
LVDS SERDES FPGA IP (intel_lvds) v23.2.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.0.0 LVDS SERDES Intel FPGA IP v20.0.1 LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel® FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
LVDS SERDES FPGA IP Release Notes

LVDS SERDES Intel FPGA IP v20.0.0

Table 6.  v20.0.0 2021.03.29
Quartus® Prime Version Description Impact
21.1
  • Optimized settings at the boundary between the FPGA fabric and I/O for LVDS SERDES IP use cases for Agilex™ 7 devices.
Recompilation of the IP is required only for Agilex™ 7 devices.
Level Two Title