LVDS SERDES Intel® FPGA IP Release Notes

ID 683575
Date 3/29/2021
Public

LVDS SERDES Intel® FPGA IP v18.1

Table 5.   v18.1 September 2018
Description Impact

For Intel® Stratix® 10 devices, the IP now supports using reference clock from other I/O banks but not from other IPs such as the IOPLL IP or the hard processor system (HPS).

If you use reference clock from other I/O bank, you must manually promote the reference clock input using the following .qsf command:
GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of top-level reference clock input port>
You are no longer limited to using only the dedicated reference clock in the IP's I/O bank.

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