LVDS SERDES Intel® FPGA IP Release Notes

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ID 683575
Date 3/29/2021
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LVDS SERDES Intel® FPGA IP Release Notes
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LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives LVDS SERDES Intel FPGA IP User Guide Archives
LVDS SERDES Intel® FPGA IP Release Notes

LVDS SERDES Intel® FPGA IP v18.1

Table 5.   v18.1 September 2018
Description Impact

For Intel® Stratix® 10 devices, the IP now supports using reference clock from other I/O banks but not from other IPs such as the IOPLL IP or the hard processor system (HPS).

If you use reference clock from other I/O bank, you must manually promote the reference clock input using the following .qsf command: 
GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of top-level reference clock input port>
 You are no longer limited to using only the dedicated reference clock in the IP's I/O bank.
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