LVDS SERDES Intel® FPGA IP v18.1
For Intel® Stratix® 10 devices, the IP now supports using reference clock from other I/O banks but not from other IPs such as the IOPLL IP or the hard processor system (HPS).
If you use reference clock from other I/O bank, you must manually promote the reference clock input using the following .qsf command:
|You are no longer limited to using only the dedicated reference clock in the IP's I/O bank.|
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