LVDS SERDES FPGA IP Release Notes

ID 683575
Date 4/07/2025
Public

LVDS SERDES Intel FPGA IP v19.4.0

Table 8.  v19.4.0 2020.04.13
Quartus® Prime Version Description Impact
20.1 Add additional delay to the pll_locked signal assertion to ensure the IP is properly locked to the PLL before IP initialization in Agilex™ 7 devices.