LVDS SERDES Intel® FPGA IP Release Notes

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ID 683575
Date 3/29/2021
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LVDS SERDES Intel® FPGA IP Release Notes
LVDS SERDES Intel® FPGA IP Release Notes x
LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives LVDS SERDES Intel FPGA IP User Guide Archives
LVDS SERDES Intel® FPGA IP Release Notes

LVDS SERDES Intel FPGA IP v19.4.0

Table 3.  v19.4.0 2020.04.13
Intel® Quartus® Prime Version Description Impact
20.1 Add additional delay to the pll_locked signal assertion to ensure the IP is properly locked to the PLL before IP initialization in Intel® Agilex™ devices. —
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