LVDS SERDES FPGA IP Release Notes

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ID 683575
Date 4/07/2025
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LVDS SERDES FPGA IP Release Notes
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LVDS SERDES FPGA IP (intel_lvds) v23.2.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0 LVDS SERDES Intel FPGA IP (intel_lvds) v23.0.0 LVDS SERDES Intel FPGA IP v20.0.1 LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel® FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition
LVDS SERDES FPGA IP Release Notes

LVDS SERDES Intel FPGA IP v19.4.0

Table 8.  v19.4.0 2020.04.13
Quartus® Prime Version Description Impact
20.1 Add additional delay to the pll_locked signal assertion to ensure the IP is properly locked to the PLL before IP initialization in Agilex™ 7 devices. —
Level Two Title