LVDS SERDES Intel® FPGA IP Release Notes

ID 683575
Date 3/29/2021
Public

LVDS SERDES Intel FPGA IP v19.4.0

Table 3.  v19.4.0 2020.04.13
Intel® Quartus® Prime Version Description Impact
20.1 Add additional delay to the pll_locked signal assertion to ensure the IP is properly locked to the PLL before IP initialization in Intel® Agilex™ devices.

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