LVDS SERDES Intel® FPGA IP Release Notes

ID 683575
Date 4/08/2024

Altera LVDS SERDES IP Core v14.0 Arria 10 Edition

Table 14.   v14.0 Arria 10 Edition August 2014
Description Impact
Added feature that creates .sdc file for generated designs (previously only for example designs)
Added support for external PLL mode
Added option to clock TX core registers using reference clock