LVDS SERDES Intel® FPGA IP Release Notes

ID 683575
Date 4/08/2024

Intel® FPGA LVDS SERDES IP Core v17.1

Table 11.  v17.1 November 2017
Description Impact
Added support for Stratix® 10 devices:
  • Duplex feature to allow transmitter and receiver channels in the same I/O bank
  • Clock phase alignment (CPA) block for improved timing closure between the periphery and the core
Renamed Altera LVDS SERDES IP core to Intel® FPGA LVDS SERDES IP core as per Intel rebranding.