LVDS SERDES Intel® FPGA IP Release Notes

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ID 683575
Date 3/29/2021
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LVDS SERDES Intel® FPGA IP Release Notes
LVDS SERDES Intel® FPGA IP Release Notes x
LVDS SERDES Intel FPGA IP v20.0.0 LVDS SERDES Intel FPGA IP v19.5.0 LVDS SERDES Intel FPGA IP v19.4.0 LVDS SERDES Intel FPGA IP v19.3.0 LVDS SERDES Intel® FPGA IP v18.1 LVDS SERDES Intel® FPGA IP v18.0 Intel FPGA LVDS SERDES IP Core v17.1 Altera LVDS SERDES IP Core v17.0 Altera LVDS SERDES IP Core v14.1 Altera LVDS SERDES IP Core v14.0 Arria 10 Edition Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives LVDS SERDES Intel FPGA IP User Guide Archives
LVDS SERDES Intel® FPGA IP Release Notes

Intel FPGA LVDS SERDES IP Core v17.1

Table 7.  v17.1 November 2017
Description Impact
Added support for Intel® Stratix® 10 devices:
  • Duplex feature to allow transmitter and receiver channels in the same I/O bank
  • Clock phase alignment (CPA) block for improved timing closure between the periphery and the core
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Renamed Altera LVDS SERDES IP core to Intel® FPGA LVDS SERDES IP core as per Intel rebranding. —
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