LVDS SERDES Intel® FPGA IP Release Notes

ID 683575
Date 4/08/2024

LVDS SERDES Intel FPGA IP (intel_lvds) v23.1.0

Table 1.  v23.1.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Added support for Agilex™ 5 FPGAs and SoCs.
Table 2.  v23.1.0 2023.12.04
Quartus® Prime Version Description Impact

Added the Transmitter Settings tab to support tx_outclock with these parameters:

  • Enable tx_outclock port
  • Desired tx_outclock phase shift (degrees)
  • Actual tx_outclock phase shift (degrees)
  • Tx_outclock division factor
Upgrade and recompilation of the IP are required only if you want to use tx_outclock.
Timing optimizations to make meeting setup and hold requirements easier. Upgrade and recompilation are not required.