AN 721: Creating an FPGA Power Tree

ID 683564
Date 6/30/2019
Public

Power Converters

After determining your FPGA power tree architecture and power requirements, you must select your power converters; every FPGA power rail input group requires a power converter. The converters must meet the minimum electrical requirements for input voltage, output voltage, and output load current.

Once you determine what converters meet the minimum electrical requirements, you must prioritize your system requirements, including size, efficiency, switching frequency, power supply noise, and cost. Optimizing some parameters or resources may degrade the performance of others. For example, increasing the switching frequency allows for a smaller system size with lower switching noise in critical frequency bands, but higher switching frequency requires more DC-DC switching and reduces efficiency by generating more switching loss. The Intel® Enpirion® power solutions use special design techniques and laterally diffused metal oxide semiconductor technology to reduce loss at high switching frequencies to minimize this trade-off.

Figure 6. Equations Relating Switching Frequency, Inductance, Capacitance, and Switch LossThese four equations can help you prioritize your system requirements. Equation a describes how inductance gets smaller with higher switching frequencies. Lower inductance enables the use of smaller, more efficient inductors. Equations b and c illustrate that input and output capacitance are smaller with higher switching frequency. Lower capacitance generally enables the use of smaller, cheaper capacitors. Equation d represents power loss, or a combination of conduction losses and switching losses. Power loss, even at high switching frequencies, can be minimized by Intel® Enpirion® devices designed to minimize CISS and COSS.

System priorities also vary depending upon the load. For example, the FPGA core power rail input (VCC) requires high power supply accuracy and low ripple to meet tight tolerance specifications, while power supply noise is a key parameter for sensitive power rails (such as transceiver voltage rails) to minimize both jitter and the bit error rate (BER).

Some power management decisions impact designs at the system level and must be considered early in the design process for successful implementation in the final system design. Some components support more advanced system power management and FPGA power reduction techniques; these components typically require special interfaces and feature sets that you should specify early in the FPGA design process. For example, you can include Enpirion® power solutions that support SmartVID in Intel® Arria® 10 10 device designs, or use Intel® Enpirion® digital controllers and PowerSoCs with a PMBus interface to implement system telemetry.

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