AN 721: Creating an FPGA Power Tree

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ID 683564
Date 6/30/2019
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Document Table of Contents
Document Table of Contents
Creating an FPGA Power Tree
Creating an FPGA Power Tree
Obtaining Power Requirements with the Early Power Estimator Power Tree Input Supply Voltage Power Rails Power Rail Inputs Power Converters Early Power Estimator Document Revision History for AN 721: Creating an FPGA Power Tree
Creating an FPGA Power Tree

Early Power Estimator

Intel added power converter groupings and recommendations to Early Power Estimator (EPE) versions 13.1 and later. The EPE tool automatically and seamlessly groups relevant FPGA power rails according to the recommendations in your selected Intel FPGA’s Pin Connection Guidelines. Based on the resulting current requirements, the EPE recommends Intel® Enpirion® power solutions that best meet your requirements. The Enpirion tab of the EPE spreadsheet shows the recommended power solution.

The Report tab of the PowerPlay EPE spreadsheet allows you to manually adjust groupings based on your design. Modifications can include: using I/O protocols at different voltages; separating sensitive rails; and implementing sequencing.

The Enpirion tab allows you to adjust the power solution recommendations based on your design priorities. Modifications can include: selecting rails to choose a low-dropout (LDO) regulator for lower noise or lower cost; and selecting devices with a “Power Good” (POK) flag for sequencing or other fault monitoring.

Figure 7. The Intel® Enpirion® Tab in the EPE Spreadsheet
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