AN 721: Creating an FPGA Power Tree

ID 683564
Date 6/30/2019
Public

Power Rail Inputs

Intel FPGAs have several inputs requiring power, but each input does not necessarily require a dedicated power converter. You can place multiple inputs together in a group with a single regulator supplying the sum total of the power. Creating a group of these inputs can reduce the space used on your PCB and reduce your system costs. When creating your FPGA power tree, you should create a group of all relevant extracted FPGA power rails for use with a single regulator.

Refer to the Pin Connection Guidelines for your selected Intel FPGA to determine what inputs you can group together; the Pin Connection Guidelines recommend a power supply block architecture for each FPGA configuration and provide details about each input pin required during hardware design.

Figure 3. Example Power Sharing Guidelines This figure shows Intel® Arria® 10 SX Device with Transceiver Data Rates ≤ 11.3 Gbps for Chip-to-Chip application Thsi figure shows a recommended Intel® Arria® 10 power tree. Refer to the Intel® Arria® 10 GX, GT, and SXDevice Family Pin Connection Guidelines.
Note:
  1. When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 in the notes in the Intel Arria 10 SX Pin Connection Guidelines.
  2. The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel Arria 10 Device Datasheet. Use the EPE tool to determine the power required for your specific design.
  3. Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements.

Intel suggests power rail groupings in the Pin Connection Guidelines for each Intel FPGA, but there are two other factors to consider when grouping your power rails. First, each of the FPGA power rail inputs in a group must have the same supply voltage requirement. This limitation is important for FPGA resource blocks such as I/O inputs that might require different voltages depending on the specific interface protocols used in your design. For example, a PCI Express® ( PCIe® ) I/O interface might require a 3 V input supply and an LVDS I/O interface might require a 2.5 V input supply; while both are I/O inputs, and the Pin Connection Guidelines simplified the I/O inputs as a single VCCIO rail, these two I/O inputs must be powered by different converters.

The second power rail grouping factor to consider is power-up sequencing. Not every FPGA or system requires power-up sequencing, but many advanced FPGAs require that power is supplied to various inputs in a specific order during system power-up. You can locate the power-up sequence guidelines for your selected Intel FPGA in the device’s Pin Connection Guidelines or Handbook. If your design requires power-up sequencing, you must ensure that grouped power rail inputs meet the sequence requirements for your Intel FPGA. You cannot provide power to a power rail if it depends upon another rail in the same group or a rail in a later group.

You can provide power to any inputs in your design individually, or in combination with another group of FPGA inputs that share their voltage and sequencing requirements.

Figure 4. Power-Up Sequence Requirement for Intel® Arria® 10 DevicesThis figure shows power-up sequence requirements for the Intel® Arria® 10 V device as described in Power Management in Intel® Arria® 10 Devices .

Once you determine your power rail input groupings, use the Early Power Estimator (EPE) spreadsheet to determine the total power required for the input group. The EPE spreadsheet combines the current requirements for each load by summing each FPGA input’s current requirement. The result are in in the Total Current (A) column in the EPE spreadsheet Report tab.

Figure 5. Power Groups in the EPE

In the EPE spreadsheet you can group inputs at any point in your design cycle, including before you start your design, or before your design is complete.

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