Other IP Cores Release Notes

ID 683556
Date 5/07/2018
Document Table of Contents

1.66. LVDS SERDES Transmitter/Receiver IP Cores v17.0

Table 68.   v17.0 May 2017
Description Impact
For the pll_phasedone signal, the asynchronous clear has been changed to synchronous clear to avoid hardware glitch.
Added support for Intel® Cyclone® 10 LP devices.