Other IP Cores Release Notes

ID 683556
Date 5/07/2018
Public
Document Table of Contents

1.19. Altera LVDS SERDES IP Core v14.0 Arria 10 Edition

Table 20.   v14.0 Arria 10 Edition August 2014
Description Impact
Added feature that creates .sdc file for generated designs (previously only for example designs) -
Added support for external PLL mode -
Added option to clock TX core registers using reference clock -