Other IP Cores Release Notes

ID 683556
Date 5/07/2018
Document Table of Contents

1.27. ALTMULT_COMPLEX IP Core v16.0

Table 28.  v16.0 May 2016
Description Impact
  • Added synchronous clear signal support for output pipeline register for Arria 10 devices.
  • Replaced Create an asynchronous Clear input check box with Clear Signal Type drop down box with the values of NONE, ACLR, and SCLR in the IP parameter editor for users selection. This change is only applicable to Arria 10 devices.