AN 829: PCI Express* Avalon® -MM DMA Reference Design

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ID 683554
Date 6/11/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.2.2. Parameter Settings for PCI Express Hard IP Variations

This reference design supports a 256-byte maximum payload size. The following tables list the values for all the parameters.

Table 1.  System Settings
Parameter Value
Number of lanes

Intel® Cyclone® 10 GX: x4

Intel® Arria® 10, Intel® Stratix® 10: x8

Lane rate

Intel® Cyclone® 10 GX: Gen2 (5.0 Gbps)

Intel® Arria® 10 Intel® Stratix® 10: Gen3 (8.0 Gbps)

RX buffer credit allocation – performance for received request

Intel® Arria® 10, Intel® Cyclone® 10 GX: Low

Intel® Stratix® 10: Not available

Table 2.  Base Address Register (BAR) Settings
Parameter Value
BAR0 64-bit prefetchable memory
BAR1 Disabled
BAR2

64-bit prefetchable memory

BAR2 is disabled for Intel® Stratix® 10

BAR3 Disabled
BAR4

64-bit prefetchable memory

BAR4 is disabled for Intel® Arria® 10 and Intel® Cyclone® 10 GX

BAR5 Disabled
Table 3.  Device Identification Register Settings
Parameter Value
Vendor ID 0x00001172
Device ID 0x0000E003
Revision ID 0x00000001
Class Code 0x00000000
Subsystem Vendor ID 0x00000000
Subsystem Device ID 0x00000000
Table 4.   PCI Express* / PCI* Capabilities
Parameter Value
Maximum payload size 256 Bytes
Completion timeout range None
Implement Completion Timeout Disable Enabled
Table 5.  Error Reporting Settings
Parameter Value
Advanced Error Reporting (AER) Enabled
ECRC checking Disabled
ECRC generation Disabled
Table 6.  Link Settings
Parameter Value
Link port number 1
Slot clock configuration Enabled
Table 7.  Message Signaled Interrupts (MSI) and MSI-XSettings
Parameter Value
Number of MSI messages requested 4
Implement MSI-X Disabled
Table size 0
Table offset 0x0000000000000000
Table BAR indicator 0
Pending bit array (PBA) offset 0x0000000000000000
PBA BAR Indicator 0
Table 8.  Power Management
Parameter Value
Endpoint L0s acceptable latency Maximum of 64 ns
Endpoint L1 acceptable latency Maximum of 1 us
Table 9.   PCIe* Address Space Setting
Parameter Value
Address width of accessible PCIe memory space 40
Level Two Title