AN 829: PCI Express* Avalon® -MM DMA Reference Design

Download
ID 683554
Date 6/11/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.2.5. Setting Up the Hardware

  1. Power down computer number 1.
  2. Plug the FPGA Development Kit card into a PCIe* slot that supports Gen2 x4 or Gen3 x8.
  3. For the Intel® Stratix® 10 10 FPGA Development Kit, connectors J26 and J27 power the card. After inserting the card into an available PCIe slot, connect 2x4- and 2x3-pin PCIe* power cables from the power supply of computer number 1 to the J26 and J27 of the PCIe* card, respectively.
  4. Connect a USB cable from computer number 2 to the FPGA Development Kit.
    The Development Kit includes an on-board Intel® FPGA Download Cable for FPGA programming.
  5. To power up FPGA Development Kit via the PCIe* slot, power on computer number 1. Alternatively, you can power up FPGA Development Kit using the external power adapter that ships with the kit.
  6. For the Intel® Cyclone® 10 GX FPGA Development Kit, an on-board programmable oscillator is the clock source for hardware components. Follow the instructions in Setting Up the Intel® Cyclone® 10 GX FPGA Programmable Oscillator to program this oscillator.
  7. On computer number 2, bring up the Intel® Quartus® Prime programmer and configure the FPGA through an Intel® FPGA Download Cable.
    Note: You must reconfigure the FPGA whenever the FPGA Development Kit loses power.
  8. To force system enumeration to discover the PCIe* device, restart computer 1.
    If you are using the Intel® Stratix® 10 GX FPGA Development Kit, you might get the following error message during BIOS initialization if the memory mapped I/O is only 4 GB: Insufficient PCI Resources Detected. To work around this issue, enable Above 4G Decoding in the BIOS Boot menu.
Related Information
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message