AN 829: PCI Express* Avalon® -MM DMA Reference Design

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ID 683554
Date 6/11/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.1. Introduction

The PCI Express* Avalon® Memory-Mapped ( Avalon® -MM) Direct Memory Access (DMA) Reference Design demonstrates the performance of the Intel® Arria® 10 , Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Hard IP for PCIe* using an Avalon® -MM interface and an embedded, high-performance DMA controller.

The design includes a Linux software driver to set up the DMA transfers. The read DMA moves data from the system memory to the on-chip or external memory. The write DMA moves data from the on-chip or external memory to the system memory. The Linux software driver also measures the system performance. This reference design allows you to evaluate the performance of the PCIe* protocol in using the Avalon® -MM interface with an embedded, high-performance DMA.

Figure 1.  PCIe* Avalon® -MM DMA Reference Design Block DiagramThis bock diagram shows both the on-chip memory and external memory options.

Section Content
DMA Reference Design Hardware and Software Requirements
Avalon -MM DMA Bridge Module Descriptions

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