1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
The PCI Express* Avalon® Memory-Mapped ( Avalon® -MM) Direct Memory Access (DMA) Reference Design demonstrates the performance of the Intel® Arria® 10 , Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Hard IP for PCIe* using an Avalon® -MM interface and an embedded, high-performance DMA controller.
The design includes a Linux software driver to set up the DMA transfers. The read DMA moves data from the system memory to the on-chip or external memory. The write DMA moves data from the on-chip or external memory to the system memory. The Linux software driver also measures the system performance. This reference design allows you to evaluate the performance of the PCIe* protocol in using the Avalon® -MM interface with an embedded, high-performance DMA.
Figure 1. PCIe* Avalon® -MM DMA Reference Design Block DiagramThis bock diagram shows both the on-chip memory and external memory options.
DMA Reference Design Hardware and Software Requirements
Avalon -MM DMA Bridge Module Descriptions
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