Visible to Intel only — GUID: sam1403481938876
Ixiasoft
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices
2.2. I/O Element Structure in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices
3.1. Guideline: VREF Sources and VREF Pins
3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards
3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing
3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down
3.6. Guideline: Maximum DC Current Restrictions
3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks
3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400
3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
Visible to Intel only — GUID: sam1403481938876
Ixiasoft
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices
The Intel® Stratix® 10 device family consists of FPGA and SoC devices. The Intel® Stratix® 10 FPGA devices have only FPGA I/O buffers. The Intel® Stratix® 10 SoC devices have FPGA I/O and HPS I/O buffers. The HPS I/O buffers in Intel® Stratix® 10 SoC devices support different I/O standards than the FPGA I/O buffers.