2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices 2.2. I/O Element Structure in Intel® Stratix® 10 Devices 2.3. Programmable IOE Features in Intel® Stratix® 10 Devices 2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices 2.5. External I/O Termination for Intel® Stratix® 10 Devices
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
1. Intel® Stratix® 10 I/O Overview
|Intel® Quartus® Prime Design Suite 22.3|
The Intel® Stratix® 10 general purpose I/O (GPIO) system consists of the I/O elements (IOE) and the GPIO Intel® FPGA IP.
- The IOEs contain bidirectional I/O buffers and I/O registers located in LVDS I/O banks.
- The GPIO IP core supports the GPIO components and features, including double data rate I/O (DDIO), delay chains, I/O buffers, control signals, and clocking.
- Two of the LVDS I/O banks are shared with the Secure Device Manager (SDM).
- For devices with Hard Processor System (HPS), three of the LVDS I/O banks are shared with the HPS SDRAM interface.
- The 3 V I/O banks do not feature I/O registers and DDIOs.
- The 3.3 V I/O bank is available in the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices.
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