Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 9/29/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.3. Timing Analysis

The Intel® Quartus® Prime software does not automatically generate the SDC timing constraints for the GPIO IP. You must manually enter the timing constraints.

Follow the timing guidelines and examples to ensure that the Timing Analyzer analyzes the I/O timing correctly.

  • To perform proper timing analysis for the I/O interface paths, specify the system level constraints of the data pins against the system clock pin in the .sdc file.
  • To perform proper timing analysis for the core interface paths, define these clock settings in the .sdc file:
    • Clock to the core registers
    • Clock to the I/O registers for the simple register and DDIO modes