Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide
ID
683517
Date
7/07/2023
Public
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3.5.2.5.1. Build and Install Netdev Driver
3.5.2.5.2. Enable VFs if SRIOV is Supported
3.5.2.5.3. Configure the Number of Channels Supported on the Device
3.5.2.5.4. Configure the MTU Value
3.5.2.5.5. Configure the Device Communication
3.5.2.5.6. Configure Transmit Queue Selection Mechanism
3.5.2.5.7. Test Procedure by Using Name Space Environment
3.5.2.5.8. PIO Test
2.1.4. MCDMA R-Tile Design Examples for Endpoint
Design Example | MCDMA Settings | Driver Support | |
---|---|---|---|
User Mode | Interface Type | ||
AVMM DMA | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVMM | Custom DPDK |
Device-side Packet Loopback | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVST 1 Port | Custom DPDK NETDEV |
Packet Generate/Check | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVST 1 Port | Custom DPDK |
PIO using MQDMA Bypass Mode | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVMM AVST 1 Port |
Custom DPDK |
Bursting Master | n/a | Custom DPDK |
|
BAM + BAS | n/a | Custom DPDK |
|
Traffic Generator/Checker | BAM + BAS | n/a | Custom DPDK |
External Descriptor Controller |
Data Mover Only |
n/a | Custom |
Note: MCDMA R-Tile PIO using Bypass design example simulation is supported in x16 and x8 topologies.. The remaining R-Tile design example simulations are not supported.
Note: MCDMA R-Tile 4x4 design example does not support simulation.