2.6. Avalon-MM DMA
This design example performs H2D and D2H multi channel DMA via Avalon-MM memory-mapped interface. The Multi Channel DMA for PCI Express IP core provides one Avalon-MM Write/Read Master port. You can allocate up to 2K DMA channels when generating this example design.
This example design contains on-chip memories to support PIO and H2D/D2H DMA operations.
For the H2D (Tx) DMA, the host populates the descriptor rings, allocates Tx packet buffers in the host memory, and fills the Tx buffers with a predefined pattern. When the application updates the Queue Tail Pointer register (Q_TAIL_POINTER), the MCDMA IP starts the H2D DMA and writes received data to the on-chip memory.
For the D2H (Rx) DMA, the host initializes the FPGA on-chip memory with a predefined pattern. The MCDMA IP reads the packet data from the on-chip memory and transmits it to the host memory.
For bidirectional DMA, H2D is started before D2H and then both DMAs operate simultaneously.
In addition, the design example enables Avalon-MM PIO master which bypasses the DMA path. It allows application to perform single, non-bursting register read/write operation with on-chip memory block.
- resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode
- MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2
- MEM – Dual port on-chip memory. One port is connected to the Avalon-MM Write Master (h2ddm_master) and the other port to Avalon-MM Read Master (d2hdm_master)
- PIO test: -o
- DMA test: -t (Tx), -r (Rx)
For a description of which driver(s) to use with this design example, refer to Driver Support.