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Ixiasoft
Visible to Intel only — GUID: qgr1647303164689
Ixiasoft
2.1.3. MCDMA F-Tile Design Examples for Endpoint
Design Example | MCDMA Settings | Driver Support | |
---|---|---|---|
User Mode | Interface Type | ||
AVMM DMA | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVMM | Custom DPDK |
Device-side Packet Loopback | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVST 1 Port | Custom DPDK Netdev |
Packet Generate/Check | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVST 1 Port | Custom DPDK |
PIO using MQDMA Bypass Mode | Multi-Channel DMA BAM + MCDMA BAM + BAS + MCDMA |
AVMM AVST 1 Port |
Custom DPDK |
Bursting Master | n/a | Custom DPDK |
|
BAM + BAS | n/a | Custom DPDK |
|
Data Mover Only | n/a | Custom DPDK |
|
Traffic Generator/Checker | BAM + BAS | n/a | Custom DPDK |
External Descriptor Controller | Data Mover Only | n/a | Custom |
For information about supported simulators, refer to Supported Simulators.
Refer to Table MCDMA IP Modes and FPGA Development Kit for Design Examples for the supported Hard IP Modes that have Design Example support.