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126.96.36.199.1. Build and Install Netdev Driver 188.8.131.52.2. Enable VFs if SRIOV is Supported 184.108.40.206.3. Configure the Number of Channels Supported on the Device 220.127.116.11.4. Configure the MTU Value 18.104.22.168.5. Configure the Device Communication 22.214.171.124.6. Configure Transmit Queue Selection Mechanism 126.96.36.199.7. Test Procedure by Using Name Space Environment 188.8.131.52.8. PIO Test
2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
Figure 2. MCDMA IP Avalon-MM Interface PIO Example Design using MCDMA Bypass mode
This design example enables Avalon-MM PIO master which bypasses the DMA path. The Avalon-MM PIO master allows application to perform single, non-bursting register read/write operation with on-chip memory.
This design example only supports PIO functionality and does not perform DMA operations (similar to the design examples in Avalon-ST PIO Using MCDMA Bypass Mode). Hence, the Avalon-MM DMA ports are not connected.
The design example includes the Multi Channel DMA for PCI Express IP Core with the parameters you specified and other supporting components:
- resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode.
- MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2.
Transfer mode option supported in test application software (perfq_app) command line:
- PIO test: -o
For a description of which driver(s) to use with this design example, refer to Driver Support.
Hardware Test Results
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