AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

ID 683511
Date 5/28/2019
Public

1.3.1. Transmitter Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane alignment (ILA) sequence.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap logic analyzer monitors the transmitter data link layer operation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message