AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

ID 683511
Date 5/28/2019
Public

1.3.3. Scrambling

With the descrambler enabled, the transport layer test pattern checker at the DAC JESD core checks the data integrity of the scrambler in the FPGA.

The Signal Tap logic analyzer monitors the operation of the TX transport layer.

Table 4.  Scrambler Test Cases
Test Case Objective Description Passing Criteria

SCR.1

Check the functionality of the scrambler using the STPL test pattern as specified in the parameter configuration.

Enable the descrambler at the DAC JESD core and the scrambler at the TX JESD204B Intel® FPGA IP.

The signals that are tapped in this test case are similar to test case TL.1.

Check the following in the DAC:
  • STPL test status
  • The jesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The STPL test status in DAC register 0x32F for all DACs does not show an error.
  • The jesd204_tx_int signal is deasserted if there is no error.

SCR.2

Verify the data transfer from digital to analog domain.

Enable the descrambler at the DAC JESD core and the scrambler at the TX JESD204B Intel® FPGA IP.

Enable the sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.

A monotone sine wave is observed on the oscilloscope.

Did you find the information on this page useful?

Characters remaining:

Feedback Message