AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

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ID 683511
Date 5/28/2019
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices

1.3.1.1. Code Group Synchronization

Table 1.  CGS Test Cases
Test Case Objective Description Passing Criteria

CGS.1

Check that /K/ characters are transmitted when sync_n is asserted.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1..0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1..0] 1

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • jesd204_tx_int

The txlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

Each lane is represented by a 32-bit data bus for the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into four octets.

Check for the following status in the AD9174 register:

  • Code Group Synchronization Status
  • The /K/ character or K28.5 (0xBC) is transmitted at each octet of the jesd204_tx_pcs_data bus when the receiver asserts the sync_n signal.
  • The jesd204_tx_pcs_kchar_data signal is asserted whenever control characters such as the /K/, /R/, /Q/, or /A/ characters are transmitted.
  • The jesd204_tx_int signal is deasserted if there is no error.
  • "Code Group Synchronization Status" for all lanes are asserted in the AD9174 register 0x470.

CGS.2

Check that /K/ characters are transmitted after sync_n is deasserted but before the start of multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1..0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1..0] 1

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • tx_sysref
  • jesd204_tx_int

The txlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

Each lane is represented by a 32-bit data bus for the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into four octets.

Check for the following errors in the AD9174 register:

  • 8b/10b Not-in-Table Error
  • 8b/10b Disparity Error
  • /K/ character transmission continues for at least one frame plus nine octets.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • “8b/10b Not-in-Table Error” and “8b/10b Disparity Error” are not asserted in the AD9174 registers 0x46E and 0x46D, respectively.
1 L is the number of lanes.
Level Two Title