1.6. Test Result Comments
In each test case, the TX JESD204B Intel® FPGA IP successfully initializes from CGS phase, ILAS phase, and until user data phase. The behavior of the TX JESD204B Intel® FPGA IP meets the passing criteria.
No data integrity issue is observed from the STPL test pattern checkers at the DAC JESD core for all the modes.
The sine wave is observed at the analog channels when the sine wave generators in the FPGA are enabled.
When the LMFCVar and LMFCDel registers at the DAC are not correctly configured, there are random STPL test failures. Hence, these registers are fine-tuned by reading the DYN_LINK_LATENCY_x register (DAC registers 0x302 and 0x303). By repeatedly power-cycling and reading the DYN_LINK_LATENCY_x register, the minimum and maximum delays across power cycles can be determined and used to calculate the LMFCVar and LMFCDel register values. For information on how to calculate these register values, refer to the AD9174 datasheet.
Setting the LMFCDel register appropriately ensures that all the corresponding data samples arrive in the same LMFC period. The LMFCVar value is then written into the receive buffer delay (RBD) register to absorb all link delay variations. This ensures that all data samples have arrived before reading. By setting the LMFCDel and LMFCVar registers to fixed values across runs and power cycles, deterministic latency is achieved.
In the deterministic latency test, deterministic latency variation of around 1 to 4 ns is observed. This variation might be attributed to the following:
- SYSREF sampling (according to the AD9174 datasheet, the amount of deterministic latency variation in subclass 1 is within ±4 DAC clock cycles at 12 GHz and ±2.5 DAC clock cycles at 6 GHz).
- Clock routing on the global clock tree in the FPGA. Potential variations are as follows:
- I/O PLL fIN variation
- I/O PLL fOUT variation
- Clock tree variation
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