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1.1. Supported Devices and Configuration Methods
1.2. Quad SPI Flash Byte-Addressing
1.3. Generic Flash Programmer Operation
1.4. Generic Flash Programmer Flow Templates ( Intel® Stratix® 10 devices)
1.5. Generic Flash Programmer Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
1.6. Generic Flash Programmer Settings Reference
1.7. Generic Flash Programmer User Guide Revision History
1.8. Generic Flash Programmer Document Archive
1.4.1. Initialization Flow Template ( Intel® Stratix® 10 Devices)
1.4.2. Program Flow Template ( Intel® Stratix® 10 Devices)
1.4.3. Erase Flow Template ( Intel® Stratix® 10 Devices)
1.4.4. Verify/Blank-Check/Examine Flow Template ( Intel® Stratix® 10 Devices)
1.4.5. Termination Flow Template ( Intel® Stratix® 10 Devices)
1.5.1. Initialization Flow Templates ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
1.5.2. Program Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
1.5.3. Erase Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
1.5.4. Verify/Blank-Check/Examine Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
1.5.5. Termination Flow Template ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
1.5.6. Programming Flow Action Properties
1.6.1. Device and Pin Options
1.6.2. More Security Options Dialog Box
1.6.3. Input Files Tab Settings (Programming File Generator)
1.6.4. Output Files Tab Settings (Programming File Generator)
1.6.5. Add Partition Dialog Box (Programming File Generator)
1.6.6. Bitstream Co-Signing Security Settings (Programming File Generator)
1.6.7. Convert Programming File Dialog Box
1.6.8. Compression and Encryption Settings (Convert Programming File)
1.6.9. SOF Data Properties Dialog Box (Convert Programming File)
1.6.10. Select Devices (Flash Loader) Dialog Box
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1.6.6. Bitstream Co-Signing Security Settings (Programming File Generator)
Option | Description |
---|---|
Bootloader | Specifies an ASCII text file in Intel® hexadecimal format that contains configuration data for programming a parallel data source, such as a configuration device or a mass storage device. The parallel data source in turn configures an SRAM-based Intel device |
Enable signing tool | Enables the signing tool that checks for a required Privacy Enhanced Mail Certificates file (.pem) for the Private key file, and a Quartus Co-Signed Firmware file (.zip) for the Co-signed firmware option. |
Private key file | Specifies the private .pem file required to sign the configuration bitstream when using the signing tool. If your .pem is password-protected, you are prompted to enter the password. |
Co-signed firmware | Specifies the firmware source (.zip) required to include the signed firmware in the configuration bitstream. |
Finalize encryption | Finalizes the configuration bitstream encryption. |
Encryption key file | Specifies the Encryption Key File (.qek) required to decrypt the configuration bitstream file. |
6 Security options not yet available for Intel® Agilex™ devices.