1.3.2. Generic Flash Programming (Convert Programming File Dialog Box)
The Factory default SFL image enables communication between the JTAG pins and the flash memory device's serial interface. The SFL is an instance of the Serial Flash Loader Intel® FPGA IP that is optimized for this function.
After generating the files, you use the Intel® Quartus® Prime Programmer to program the flash, which in turn configures the FPGA via AS configuration.
Generic flash programming with the Convert Programming File dialog box includes the following high level steps that this section describes in detail:
- Step 1: Generate Primary Device Programming Files—use the Intel® Quartus® Prime Assembler to generate the .sof FPGA configuration file.
- Step 2: Generate Secondary Programming Files (Convert Programming Files)—use the Convert Programming File dialog box to generate the .jic that you program into your flash memory device to store .sof configuration data.
- Step 3: Program the Flash Memory Device—use the Intel® Quartus® Prime Programmer and connected Intel FPGA download cable to program the .jic configuration data into the flash memory device and the .sof into the FPGA via Active Serial JTAG configuration.
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