Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

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ID 683487
Date 12/14/2020
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1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes x
1.1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v20.4 1.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v18.0 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v17.1 1.4. Intel® Arria® 10 Hard IP for PCI Express* IP Core v17.0 1.5. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.1 1.6. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.0 1.7. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.1 1.8. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.0 1.9. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.1 1.10. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.0 Intel® Arria® 10 Edition 1.11. Intel® Arria® 10 Hard IP for PCI Express* IP Core v13.1 Arria 10 Edition
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

1.5. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.1

Table 5.  16.1 October 2016
Description Impact
Added parameter to select preset for Phase2 and Phase3 far-end TX equalization. Better control of signal quality.
For the Avalon-MM with DMA interface, increased the maximum DMA transfer size to 1 megabyte (MB) for both the 128- and 256-bit interfaces. Reduces the number of descriptors required to transfer data.
For the Single-Root I/O Virtualization (SR-IOV) interface, changed support for the 128-bit interface from preliminary to final. You can use the 128-bit interface in production designs.
For the SR-IOV interface, added licensing requirement. You must purchase a license to use this variant in hardware.
For the SR-IOV interface, added Intel FPGA IP Evaluation Mode support. Allows you to generate time-limited device programming files for the SR-IOV interface.
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