1.5. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.1
|Added parameter to select preset for Phase2 and Phase3 far-end TX equalization.||Better control of signal quality.|
|For the Avalon-MM with DMA interface, increased the maximum DMA transfer size to 1 megabyte (MB) for both the 128- and 256-bit interfaces.||Reduces the number of descriptors required to transfer data.|
|For the Single-Root I/O Virtualization (SR-IOV) interface, changed support for the 128-bit interface from preliminary to final.||You can use the 128-bit interface in production designs.|
|For the SR-IOV interface, added licensing requirement.||You must purchase a license to use this variant in hardware.|
|For the SR-IOV interface, added Intel FPGA IP Evaluation Mode support.||Allows you to generate time-limited device programming files for the SR-IOV interface.|
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